Accelerometer and its fabrication technique

ABSTRACT

An accelerometer has E-shaped resilient beams to isolate stress and reduce deformation. A top cap silicon wafer and a bottom cap silicon wafer are both coupled with a measurement mass to form a capacitor. The measurement mass has a mass, range-of-motion stops, and resilient beams located within a support frame. The range-of-motion stops are coupled to the support frame by connection beams, and the mass is coupled with the range-of-motion stops by groups of E-shaped resilient beams. The ends of each resilient beam are connected to the range-of-motion stops, and the middle of each resilient beam is connected to the mass.

CROSS-REFERENCE

This application is a division of U.S. application Ser. No. 14/031,613 and claims priority from Chinese Patent Application No. 201210356922.7 filed Sep. 21, 2012 entitled An Accelerometer and its Fabrication Technique, the entirety of which is incorporated herein by reference.

TECHNICAL FIELD

This invention relates to a sensor, particularly to an accelerometer.

BACKGROUND

Nowadays, accelerometers have been used in various applications, such as, measuring the magnitude of earthquake and gathering seismic data, detecting the magnitude of collision during a car collision, and detecting the tilting direction and angle of a mobile phone or a game console. As the micro-electro-mechanical systems (MEMS) technology continues to progress, many nano-scale accelerometers have been widely commercially used.

There are two kinds of accelerometers which are commonly used: piezo resistive accelerometers and capacitive accelerometers. Piezoresistive accelerometer, such as Chinese invention patent application with Publication No. CN1748146 and Publication Date of Mar. 15, 2006, usually comprises mass and beams; piezo elements are provided on the beam. The mass moves according to the acceleration, and causes the beam to deform, which also causes the change of resistance. However, under situations when there is no acceleration or the acceleration magnitude is relatively small, the beam will not deform significantly. And there is no significant change in resistance. The accelerometer can only detect acceleration when the magnitude of acceleration is large enough to cause the deformation of the beam. Therefore, such accelerometer has low accuracy.

Capacitive accelerator, such as U.S. Pat. No. 6,805,008, with Publication Date of Oct. 19, 2004, also includes beam and mass. When the acceleration is present, the frame of the accelerometer will move according to the acceleration direction, but due to inertia, there is little displacement for the mass. Thus, the gap distance change between the mass and another electrode causes a change in capacitance. Both kinds of accelerometers are manufactured by micro fabrication technique and have the characteristics of small size and low manufacturing cost. However, the beams are resilient beams, and there are only four beams connecting the mass with the frame. Thus, when the outer frame moves, the displacement of each beam is relatively large. Also, each beam will not create a uniform displacement and deformation, which leads to unsymmetrical vibrational modes.

Furthermore, when packaging the above-mentioned capacitive accelerometer with other microelectronic modules to form an integrated circuit, a package-induced stress is generated due to the difference of coefficients of thermal expansion between different materials. The package-induced stress will directly affect the performance of each component. Compared with other components, MEMS components is more sensible to package-induced stress due to its small size and moveable parts. The package-induced stress may cause a deformation of components in the accelerometer, which leads to inaccurate acceleration detection, and lowers the accelerometer's stability and reliability.

SUMMARY

The present invention is intended to overcome the shortages of the existing accelerometers, and to provide an accelerometer with low effect on package-induced stress and has relatively high stability and reliability.

The present invention provides an accelerometer, comprising a measurement mass, a top cap silicon wafer and a bottom cap silicon wafer which both are coupled with the said measurement mass; the measurement mass comprises a support frame, a mass, a plurality of range-of-motion stops and resilient beams. The mass, the range-of-motion stops and the resilient beams are located within the support frame; the range-of-motion stops are located away from the support frame, and coupled to the support frame by connection beams. The mass is coupled with the range-of-motion stops by resilient beams; there are several groups of resilient beams, each resilient beam has an E-shape structure; the two-end beams of each resilient beam are connected to the range-of-motion stops; and the middle beam of the resilient beam is connected to the mass.

The present invention also has the following additional features:

Several recesses are provided on the mass; there are several range-of-motion stops, each being located within the recess.

A gap is formed between the mass and each range-of-motion stop.

Each resilient beam is provided within the gap space between the support frame and the mass; the resilient beams can move freely within the gap space.

The middle beam of each resilient beam is located across the midline of the mass.

Each connection beam is provided at the corner of the range-of-motion stop; each connection beam is coupled with the internal corner of the frame.

The measurement mass has a double side silicon on insulator (SOI) structure, which includes top silicon layer, middle silicon layer, and bottom silicon layer; a silicon dioxide layer is provided between two silicon layers. The double side silicon on insulator structure is also referred as double side SOI structure.

A plurality of the resilient beams, the range-of-motion stops, and the connection beams are respectively symmetrically formed in the top silicon layer and the bottom silicon layer to compose a double layer structure.

Electrodes are respectively provided on the measurement mass, the top cap silicon wafer and the bottom cap silicon wafer.

In accordance with the present invention to provide a fabrication technique for the accelerometer, including the following steps:

Step 1, use photolithography, deep etching and etching to form a plurality of holes penetrating from the top silicon layer and bottom silicon layer to the middle silicon layer of the double side SOI silicon wafer;

Step 2, deposit polycrystalline silicon in the holes to fill up the holes in order to form an electric circuit; then grow a silicon dioxide layer on the surfaces of the top silicon layer and bottom silicon layer of the double side SOI silicon wafer; and polish the surface;

Step 3, use photolithography, deep etching and etching to form a plurality of resilient E-shaped beams, range-of-motion stops and connection beams in the top silicon layer and the bottom silicon layer of the double side SOI silicon wafer; then use thermal oxidation to grow silicon dioxide on the exposed surfaces of the resilient E-shaped beams, the range-of-motion stops and the connection beams; or use chemical vapor deposition(CVD) method to dispose a layer of silicon dioxide on the exposed surfaces of the resilient E-shaped beams, the range-of-motion stops and the connection beams;

Step 4, use photolithography and etching to remove the exposed silicon dioxide in on the middle silicon layer, and deep etch the middle silicon layer to a certain depth;

Step 5, simultaneously perform etching in the horizontal and vertical directions to the middle silicon layer located between the frame and the mass in order to form free-moving resilient beams;

Step 6, etching to remove the exposed silicon dioxide layer;

Step 7, perform a one-step bonding to the top cap silicon wafer, the processed double side SOI silicon wafer, and the bottom cap silicon wafer.

According to the present invention, the fabrication technique for the accelerometer further includes the following steps:

The fabrication technique for the top cap silicon wafer and bottom cap silicon wafer further comprises:

A. use photolithography, deep etching and etching to form a through hole on the top cap silicon wafer or the bottom cap silicon wafer;

B. use photolithography, deep etching and etching to respectively form a recess area on each bonding surface of the top cap silicon wafer and bottom cap silicon wafer;

C. clean the top cap wafer and bottom cap wafer before bonding with the double side SOI silicon wafer;

D. after bonding with the double side SOI silicon wafer, deposit metal on the surface of top cap silicon wafer and bottom cap silicon wafer to form electrodes; and deposit metal on the surface of double side SOI silicon wafer through the through hole formed on the top cap silicon wafer or bottom cap silicon wafer to form an electrode from the through hole.

In the fabrication technique disclosed in the present invention, the silicon dioxide layers serve the purpose of protecting the silicon layers, which are covered up by the silicon dioxide layers, from etching or corrosion.

The said depth etching and etching method includes one or more from the following methods: dry etching or wet etching; the said dry etching comprises: silicon deep reactive-ion etching and reactive-ion etching. The etchant for etching the silicon layer comprises one kind or a combination of the following etchants: potassium hydroxide, tetramethylammonium hydroxide, ethylenediamine pyrocatechol or gaseous xenon difluoride.

The etchant for etching the silicon dioxide layer comprises one kind or a combination of the following etchants: buffered hydrofluoric acid, 49% hydrofluoric acid or gaseous hydrogen fluoride. The said silicon dioxide layer can also be removed by reactive-ion etching of the dry etching method.

In accordance to the present invention, the accelerometer and its fabrication technique has the following advantages. First of all, by adding the range-of-motion stops between the mass and the support frame, the invention effectively reduces the effect of the package-induced stress on the mass and resilient beams during chip packaging, so as to improve the stability and reliability of the accelerometer. By adding the range-of-motion stops between the mass and the frame, the invention also reduces the effect of the stress generated by temperature and gas pressure in the working environment on the accelerometer. Also, the middle beams of the resilient beams cross through the midline of the mass, which endows the accelerometer with symmetrical and stable structure. Furthermore, the fabrication technique of the present accelerometer utilizes double side SOI silicon wafer and one-step bonding technique for three pieces of silicon wafer. By etching the resilient beam and the mass on the double side SOI silicon wafer, the components can be accurately aligned and forms a highly symmetrical structure. Compared with the prior art, which uses bonding technique to fabricate the dual-layer beams, the accelerometer fabricated by the present technique has high accuracy and small error; the throughput yield is also significantly increased. Since the etching technique is relatively simple, the present fabrication technique also has a high productive efficiency and low manufacturing cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a structure scheme of the present invention;

FIG. 2 is a perspective view of the measurement mass in the present invention;

FIG. 3 is a top view of the measurement mass in the present invention;

FIG. 4 is a diagram of step 1 to step 3 of the fabrication technique in accordance with the present invention;

FIG. 5 is a diagram of step 4 to step 6 of the fabrication technique in accordance with the present invention;

FIG. 6 is a diagram of step 7 of the fabrication technique in accordance with the present invention.

DETAILED DESCRIPTION

The present invention will be described in further detail below with reference to the drawings and specific embodiments.

With reference to FIG. 1, an accelerometer comprises: measurement mass 1, top cap silicon wafer 2 and bottom cap silicon wafer 3, which both are coupled with the measurement mass 1; electrodes 4 are respectively provided on the measurement mass 1, the top cap silicon wafer 2, and the bottom cap silicon wafer 3. The measurement mass 1 has a double side SOI structure, it comprises top silicon layer 5, middle silicon layer 6, and bottom silicon layer 7; silicon dioxide layers 8 are provided between two silicon layers.

With reference to FIGS. 2 and 3, the measurement mass 1 comprises support frame 11, a plurality of range-of-motion stops 12, resilient beams 13, and a mass 14. The range-of-motion stops 12, resilient beams 13 and mass 14 are located within the support frame 11; the range-of-motion stops 12 are located away from the support frame 11, and coupled with the support frame 11 by connection beams 15. The mass 14 is coupled with the range-of-motion stops 12 by resilient beams 13. There are several groups of resilient beams 13; each resilient beam 13 has an E-shape structure, the two side beams 131 of each resilient beam 13 are connected to the range-of-motion stops 12; and the middle beam 132 of the resilient beam 13 is connected to the mass 14. Several recesses 141 are provided on the mass 14. There are several range-of-motion stops 12; and each range-of-motion stop 12 is located within the recess 141; A gap is also formed between the mass 14 and each range-of-motion stop 12.

With reference to FIGS. 1 and 2, the measurement mass 1 can be separated into top silicon layer 5, middle silicon layer 6, and bottom silicon layer 7. Multiple groups of range-of-motion stops 12, resilient beams 13, and connection beams 15 are respectively symmetrically formed in the top silicon layer 5 and the bottom silicon layer 7.

With reference to FIGS. 2 and 3, preferably, the mass 14 is a rectangular body. The resilient beams 13 are provided within the gap space between the support frame 11 and the mass 14; the resilient beams 13 can move freely within the gap space. Each resilient beam 13 has an E-shape structure. Preferably, each layer contains four groups of resilient beams 13, range-of-motion stops 12, and connection beams 15. Each group of resilient beam 13 is respectively provided along four sides of the mass 14. Within each group, the two-end beams 131 of the resilient beam 13 are coupled with the range-of-motion stops; and the middle beam 132 of the resilient beam 13 is coupled with the mass 14. Each middle beam 132 is located across the midline of the mass 14. Each connection beam 15 is respectively provided at the corner of the range-of-motion stop 12, and coupled with the internal corner of the support frame 11. The overall structure of the measurement mass 1 is symmetrical, which makes the overall design more balanced, stable, and more accurate for measuring the direction of acceleration. The shape of the mass 14 in the present invention however is not limited to a rectangular shape; it can also be other shapes, such as hexagon, octagon, circle, etc. The arrangement of resilient beams 13, range-of-motion stops 12, and connection beams 15 are also not limited to a two layer structure, where each layer contains four groups of resilient beams 13, range-of-motion stops 12, and connection beams 15; it can also be a structure containing multiple layers and multiple groups.

With reference to FIGS. 1 and 2, during the acceleration measurement process, the support frame 11 will displace towards the acceleration direction. The resilient beams 13 will also have a certain amount of displacement. However, due to inertia, the magnitude of displacement of the mass 14 is relatively small. According to equation C=εA/d, where the capacitance between two parallel conductive plates equal to the permittivity of material (ε)times area (A) divide by the separation distance (d). When displacement is generated due to acceleration, the distance between the mass 14, the top cap silicon wafer 2 and bottom cap silicon wafer 3 changes. Therefore, the capacitance between the measurement mass 1, the top cap silicon wafer 2 and the bottom cap silicon wafer 3 also changes. The integrated circuit can calculate the measured acceleration based on the change of capacitance. After the acceleration disappears, the resilient beams 13 will return to its original state, which returns the capacitance between the mass 14, the top cap silicon wafer 2 and the bottom cap silicon wafer 3 to a constant value.

With reference to FIGS. 2 and 3, during the packaging process of the accelerometer, the support frame 11 will experience the maximum amount of package-induced stress, and may be easily deformed. The present invention provides connection beams 15, which are connected to the range-of-motion stops 12, on the four internal corners of the support frame 11. Even if the support frame 11 deforms due to the package-induced stress, and the connection beams 15 may also deform by a certain amount, the deformation will not affect the range-of-motion stops 12 since the connection beams 15 are resilient. The deformation certainly will not affect the mass 14 and the resilient beams 13 connected to the mass 14. Thus, the capacitance between the mass 14, the top cap silicon wafer 2, and the bottom cap silicon wafer 3 is relatively stable. When there is no acceleration, the capacitance between the mass 14, the top cap silicon wafer 2, and the bottom cap silicon wafer 3 is constant and equal. When there is acceleration, the displacement of each resilient beam 13 is mostly uniform. The accelerometer is capable of measuring vibration and acceleration more effectively and providing more accurate measurements.

Next, the fabrication technique for the accelerometer disclosed in the present invention is described with reference to FIG. 4, FIG. 5, and FIG. 6, which includes the following steps:

Step 1: coat a layer of photoresist on the surface of the top silicon layer 5 and the bottom silicon layer 7 of the double side SOI silicon wafer. Then expose the top silicon layer 5 and the bottom silicon layer 7 according to certain patterns, and develop the patterns with developers to make the patterns apparent. After that, etch the exposed part of the top silicon layer 5 and the bottom silicon layer 7 to the silicon dioxide layer 8 by using the deep reactive ion etching. The exposed part of the silicon dioxide layer 8 is further etched using the dry reactive ion etching or buffered hydrofluoric acid. And form a plurality of holes, which are deep to the middle silicon layer 6. The photoresist is removed afterwards.

Step 2: deposit polycrystalline silicon to fill up the holes and to form an electric circuit; grow a layer of silicon dioxide on the surfaces of the top silicon layer 5 and the bottom silicon layer 7. Then polish the surfaces of the top silicon layer 5 and the bottom silicon layer 7 by chemical or mechanical polishing technique in order to meet the smoothness requirement.

Step 3: coat a layer of photoresist on the surface of the top silicon layer 5 and the bottom silicon layer 7. Then expose the top silicon layer 5 and the bottom silicon layer 7 according to certain patterns, and develop the patterns with developers to make the patterns apparent. First etch the exposed part of the grown silicon dioxide layer using dry reactive ion etching or buffered hydrofluoric acid. Then etch the top silicon layer 5 and the bottom silicon layer 7 to the silicon dioxide layer 8 using deep reactive ion etching. Finally etch the exposed part of the silicon dioxide layer using dry reactive ion etching or buffered hydrofluoric acid, which forms a plurality of resilient beams 13, range-of-motion stops 12, and connection beams 15. A layer of silicon dioxide is either grown or chemical vapor deposited (CVD) on top of the resilient beams 13, range-of-motion stops 12, and connection beams 15.

Step 4: etch to remove the exposed part of the silicon dioxide layer 8 by using dry etching method. Then deep etch the middle silicon layer 6 to a certain depth by using silicon deep reactive ion etching or gaseous xenon difluoride.

Step 5: etch the middle silicon layer 6, which has been etched to a certain depth, in both horizontal and vertical directions by using potassium hydroxide, or tetramethylammonium hydroxide, or ethylenediamine pyrocatechol, or gaseous xenon difluoride. The etching time is controlled based on the size of the region to be etched away in the middle silicon layer 6. After the middle silicon layer 6 is etched, two layers of free-moving resilient beams 13, range-of-motion stops 12, and connection beams 15 are formed.

Step 6: etch away the silicon dioxide exposed on the silicon surface by using buffered hydrofluoric acid, 49% hydrofluoric acid, or gaseous hydrogen fluoride.

Step 7: Perform a one-step-bonding to the top cap silicon wafer, the processed double side SOI silicon wafer and the bottom cap silicon wafer.

The fabrication technique of the accelerometer disclosed in the present invention further includes the following steps:

The fabrication technique for the top cap silicon wafer and bottom cap silicon wafer also includes:

A. before bonding with the double side SOI silicon wafer, coat photoresist on the top cap silicon wafer 2 or the bottom cap silicon wafer 3; then expose according to certain patterns, and develop with developer to make the patterns apparent. Etch the exposed portion of the top cap silicon wafer 2 or the bottom cap silicon wafer 3 until the silicon dioxide layer 8 is exposed by using deep reactive ion etching method, potassium hydroxide, tetramethyl ammonium hydroxide, or ethylenediamine phosphorus hydroquinone. Then further etch the exposed portion of the silicon dioxide layer 8 to form a through hole by using buffered hydrofluoric acid, 49% hydrofluoric acid, or gaseous hydrogen fluoride. The photoresist is removed in the end.

B. coat photoresist on the top cap silicon wafer 2 and the bottom cap silicon wafer 3; then expose according to certain patterns, and develop with developers to make the patterns apparent. Respectively etch the exposed portion of the top cap silicon wafer 2 and the bottom cap silicon wafer 3 to a certain depth by using deep reactive ion etching method, potassium hydroxide, tetramethylammonium hydroxide, or ethylenediamine pyrocatechol, to thereby respectively form a recess area on each bonding surface of top cap silicon wafer 2 and bottom cap silicon wafer 3.

C. clean the top cap silicon wafer 2 and the bottom cap silicon wafer 3 before bonding with the double side SOI silicon layer.

D. after boding with the double side SOI silicon wafer, deposit metal on the surfaces of the top cap silicon wafer 2 and bottom cap silicon wafer 3 to form electrodes 4; deposit metal on the surface of double side SOI silicon wafer through the through hole formed on either the top cap silicon wafer 3 or bottom cap silicon wafer 4 to form an electrode 4 through the through hole.

The silicon dioxide layers mentioned in the above fabrication technique serve the purpose of protecting the silicon layers, which are covered up by the silicon dioxide layers, from etching or corrosion.

The deep etching method and etching method mentioned in the present invention includes one or more of the following methods: dry etching or wet etching. The said dry etching includes, silicon deep reactive-ion etching and reactive-ion etching.

The material, equipment, and techniques used in the present invention have been disclosed by prior arts, but the accelerometer is dramatically improved by using these material and techniques, particularly by using the double side SOI silicon wafer. The resilient beams 13 and the mass 14, formed by etching the double side SOI silicon wafer, are accurately aligned and form a high symmetrical structure. Compared with the prior art, which fabricates the two level beams by bonding, the accelerometer fabricated using the present technique has higher accuracy and small error; the throughput yield also increases. Since the etching technique process is relatively simple, the present fabrication technique process also has high production efficiency and low manufacturing cost. Furthermore, the geometry and vibration modes of the present accelerometer are symmetrical, which further increases the measurement accuracy. By adding the range-of-motion stops 12 between the mass 14 and the support frame 11, the present invention not only reduces the effect of package-induced stress on the accelerometer while packaging; it also reduces the effect of thermal stress induced by the temperature change in the working environment on the accelerometer. Therefore, the present accelerometer is more stable. 

1. An accelerometer fabrication technique comprising the following steps: (i) forming, by use of photolithography, deep etching and etching, a plurality of holes penetrating from a top silicon layer and a bottom silicon layer to a middle silicon layer of a double-sided silicon on insulator (SOI) silicon wafer; (ii) depositing polycrystalline silicon in the holes to fill up the holes, then growing a silicon dioxide layer on surfaces of the top silicon layer and the bottom silicon layer of the double-sided SOI silicon wafer; (iii) forming, by use of photolithography, deep etching and etching, a plurality of resilient E-shaped beams, range-of-motion stops and connection beams in the top silicon layer and the bottom silicon layer of the double side SOI silicon wafer, then growing, by use of thermal oxidation, silicon dioxide on exposed surfaces of the resilient E-shaped beams, the range-of-motion stops and the connection beams, or depositing, by use of chemical vapor deposition (CVD), a layer of silicon dioxide on exposed surfaces of the resilient E-shaped beams, the range-of-motion stops and the connection beams; (iv) removing, by use of photolithography and etching, the exposed silicon dioxide in the middle silicon layer, and deep etching the middle silicon layer to a certain depth; (v) corroding the middle silicon layer located between a support frame and a mass in order to form free-moving resilient beams; (vi) removing by etching the exposed silicon dioxide layer; and (vii) bonding together in one-step the top cap silicon wafer, the processed double-sided SOI silicon wafer, and the bottom cap silicon wafer.
 2. An accelerometer fabrication technique according to claim 1, wherein the fabrication technique for the top cap silicon wafer and bottom cap silicon wafer further comprises: A. forming, by use of photolithography, deep etching and etching, a through hole on the top cap silicon wafer or the bottom cap silicon wafer; B. forming, by use of photolithography, deep etching and etching, a recess area on each bonding surface of the top cap silicon wafer and the bottom cap silicon wafer; C. before the bonding step, cleaning the top cap silicon wafer and the bottom cap silicon wafer; D. after the bonding step, depositing metal on the surfaces of the top cap silicon wafer and the bottom cap silicon wafer to form electrodes, and depositing metal on the surface of the double-sided SOI silicon wafer through the through hole formed on the top cap silicon wafer or the bottom cap silicon wafer, to form an electrode from the through hole.
 3. An accelerometer fabrication technique according to claim 1, wherein the deep etching or etching method is selected from one or more following methods: dry etching or wet etching; and the dry etching method comprises silicon deep reactive ion etching or reactive ion etching.
 4. An accelerometer fabrication technique according to claim 2, wherein the deep etching or etching method is selected from one or more following methods: dry etching or wet etching; and the dry etching method comprises silicon deep reactive ion etching or reactive ion etching.
 5. An accelerometer fabrication technique according to claim 1, wherein the etchant for etching the silicon layer comprises one or more of the following etchants: potassium hydroxide, tetramethylammonium hydroxide, ethylenediamine pyrocatechol, or gaseous xenon difluoride.
 6. An accelerometer fabrication technique according to claim 1, wherein the etchant for etching the silicon dioxide layer comprises one or more of the following etchants: buffered hydrofluoric acid, 49% hydrofluoric acid, or gaseous hydrogen fluoride.
 7. A method for fabricating an accelerometer, comprising: (i) forming a plurality of holes penetrating from a top silicon layer and a bottom silicon layer to a middle silicon layer of a double-sided silicon on insulator (SOI) silicon wafer; (ii) depositing polycrystalline silicon in the holes, then growing a silicon dioxide layer on surfaces of the top silicon layer and the bottom silicon layer of the double-sided SOI silicon wafer; (iii) forming a plurality of resilient E-shaped beams, range-of-motion stops and connection beams in the top silicon layer and the bottom silicon layer of the double side SOI silicon wafer, then growing silicon dioxide on exposed surfaces of the resilient E-shaped beams, the range-of-motion stops and the connection beams, or depositing a layer of silicon dioxide on exposed surfaces of the resilient E-shaped beams, the range-of-motion stops and the connection beams; (iv) removing the exposed silicon dioxide in the middle silicon layer, and deep etching the middle silicon layer to a certain depth; (v) corroding the middle silicon layer located between a support frame and a mass in order to form free-moving resilient beams; (vi) removing the exposed silicon dioxide layer; and (vii) bonding together in one-step the top cap silicon wafer, the processed double-sided SOI silicon wafer, and the bottom cap silicon wafer. 